The present invention relates to a semiconductor device and package having fine RDL pitch and improved signal integrity.
Cost and size reduction is driving packaging industry to new measures and approaches. Wafer level packaging is one approach, which the packaging industry is looking into for size and cost reduction.
For example, Fan-Out Wafer Level Packaging (FOWLP), which is known in the art, integrates at least two individual integrated circuit (IC) dies in a side-by-side configuration into one molded semiconductor package having fan-out redistribution layer (RDL) and post passivation interconnection (PPI). The two IC dies are interconnected to each other through the RDL. FOWLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FCBGA) packages.
However, as more and more functions are incorporated into one single IC die, the die-to-die signal points have dramatically increased. The increased die-to-die signal points results in considerable loss of routing space in the redistribution layer (RDL). Currently, at most three to four signal traces can be arranged between two adjacent landing pads due to the relatively large size of each landing pad. There is no enough room for disposing the shielding traces. This adversely influences the signal integrity in high-speed applications because of crosstalk between signals.
Accordingly, there is a need in this industry to provide an improved wafer level package with fine RDL pitch and improved signal integrity.